The TPi2.4's NAND consists of 1024 eraseblocks, each consisting of 64 pages, each page is 2,048 bytes. UBI calls these "physical eraseblocks" (PEBs). A "logical eraseblock" (LEB) is a PEB minus 2 pages (for the erase counter and volume ID headers), so LEBs are 124KiB while PEBs are 128KiB. The 1024 eraseblocks are allocated as follows: - 8 EBs for the bootloader code - 40 EBs reserved for bad block handling - 2 EBs for the UBI layout volume (essentially the "partition table") - 1 EB for the bootloader environment - 370 EBs for the active firmware - 370 EBs for the incoming (or previous) firmware - 230 EBs for the overlay - 3 EBs unused